VPSLLVQ - Packed Shift Left Logical Variable Qword
VPSLLVQ xmm1, xmm2, xmm3/m128 (V2
__m128i _mm_sllv_epi64(__m128i a, __m128i b)
VPSLLVQ xmm1{k1}{z}, xmm2, xmm3/m128/m64bcst (V5+VL
__m128i _mm_mask_sllv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b)
__m128i _mm_maskz_sllv_epi64(__mmask8 k, __m128i a, __m128i b)
For each QWORD, set (1) << (2) to (3). Emptied lower bits are zeroed.
VPSLLVQ ymm1, ymm2, ymm3/m256 (V2
__m256i _mm256_sllv_epi64(__m256i a, __m256i b)
VPSLLVQ ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst (V5+VL
__m256i _mm256_mask_sllv_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b)
__m256i _mm256_maskz_sllv_epi64(__mmask8 k, __m256i a, __m256i b)
For each QWORD, set (1) << (2) to (3). Emptied lower bits are zeroed.
VPSLLVQ zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst (V5
__m512i _mm512_sllv_epi64(__m512i a, __m512i b)
__m512i _mm512_mask_sllv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b)
__m512i _mm512_maskz_sllv_epi64(__mmask8 k, __m512i a, __m512i b)
For each QWORD, set (1) << (2) to (3). Emptied lower bits are zeroed.
x86/x64 SIMD Instruction List
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