VPSRLVQ - Packed Shift Right Logical Variable Qword

VPSRLVQ xmm1, xmm2, xmm3/m128    (V2
__m128i _mm_srlv_epi64(__m128i a, __m128i b)
VPSRLVQ xmm1{k1}{z}, xmm2, xmm3/m128/m64bcst    (V5+VL
__m128i _mm_mask_srlv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b)
__m128i _mm_maskz_srlv_epi64(__mmask8 k, __m128i a, __m128i b)

For each QWORD, set (1) >> (2) to (3). Emptied upper bits are zeroed.
VPSRLVQ ymm1, ymm2, ymm3/m256    (V2
__m256i _mm256_srlv_epi64(__m256i a, __m256i b)
VPSRLVQ ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst    (V5+VL
__m256i _mm256_mask_srlv_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b)
__m256i _mm256_maskz_srlv_epi64(__mmask8 k, __m256i a, __m256i b)

For each QWORD, set (1) >> (2) to (3). Emptied upper bits are zeroed.
VPSRLVQ zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst    (V5
__m512i _mm512_srlv_epi64(__m512i a, __m512i b)
__m512i _mm512_mask_srlv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b)
__m512i _mm512_maskz_srlv_epi64(__mmask8 k, __m512i a, __m512i b)

For each QWORD, set (1) >> (2) to (3). Emptied upper bits are zeroed.

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