VCVTPS2UQQ - ConVerT Packed Single to Unsigned Qword Qword
float -> unsigned QWORD
rounding controlled by {er} or MXCSR
VCVTPS2UQQ xmm1{k1}{z}, xmm2/m64/m32bcst (V5+DQ+VL
__m128i _mm_cvtps_epu64(__m128 a)
__m128i _mm_mask_cvtps_epu64(__m128i s, __mmask8 k, __m128 a)
__m128i _mm_maskz_cvtps_epu64(__mmask8 k, __m128 a)
VCVTPS2UQQ ymm1{k1}{z}, xmm2/m128/m32bcst (V5+DQ+VL
__m256i _mm256_cvtps_epu64(__m128 a)
__m256i _mm256_mask_cvtps_epu64(__m256i s, __mmask8 k, __m128 a)
__m256i _mm256_maskz_cvtps_epu64(__mmask8 k, __m128 a)
VCVTPS2UQQ zmm1{k1}{z}, ymm2/m256/m32bcst{er} (V5+DQ
__m512i _mm512_cvtps_epu64(__m256 a)
__m512i _mm512_mask_cvtps_epu64(__m512i s, __mmask8 k, __m256 a)
__m512i _mm512_maskz_cvtps_epu64(__mmask8 k, __m256 a)
__m512i _mm512_cvt_roundps_epu64(__m256 a, int r)
__m512i _mm512_mask_cvt_roundps_epu64(__m512i s, __mmask8 k, __m256 a, int r)
__m512i _mm512_maskz_cvt_roundps_epu64(__mmask8 k, __m256 a, int r)
x86/x64 SIMD Instruction List
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