mnemonic | where ? | ||||
---|---|---|---|---|---|
Q | D | W | B | ||
lower 64-bit | lower 32-bit | lower 16-bit | lower 8-bit | ||
add |
KADD? k1, k2, k3 k1 ← k2 + k3 |
(V5+BW | (V5+BW | (V5+DQ | (V5+DQ |
and |
KAND? k1, k2, k3 k1 ← k2 & k3 |
(V5+BW | (V5+BW | (V5 | (V5+DQ |
and not |
KANDN? k1, k2, k3 k1 ← (~k2) & k3 |
(V5+BW | (V5+BW | (V5 | (V5+DQ |
move from k register/memory |
KMOV? k1, k2/mem k1 ← k2/mem |
(V5+BW mem = m64 |
(V5+BW mem = m32 |
(V5 mem = m16 |
(V5+DQ mem = m8 |
move from GP register |
KMOV? k1, reg k1 ← reg |
(V5+BW# reg = r64 |
(V5+BW reg = r32 |
(V5 reg = r32 |
(V5+DQ reg = r32 |
move to memory |
KMOV? mem, k1 mem ← k1 |
(V5+BW mem = m64 |
(V5+BW mem = m32 |
(V5 mem = m16 |
(V5+DQ mem = m8 |
move to GP register |
KMOV? reg, k1 reg ← k1 |
(V5+BW# reg = r64 |
(V5+BW reg = r32 |
(V5 reg = r32 |
(V5+DQ reg = r32 |
not |
KNOT? k1, k2 k1 ← ~k2 |
(V5+BW | (V5+BW | (V5 | (V5+DQ |
or |
KOR? k1, k2, k3 k1 ← k2 | k3 |
(V5+BW | (V5+BW | (V5 | (V5+DQ |
or test |
KORTEST? k1, k2 *1 |
(V5+BW | (V5+BW | (V5 | (V5+DQ |
shift left |
KSHIFTL? k1, k2, imm8 k1 ← k2 << imm8 |
(V5+BW | (V5+BW | (V5 | (V5+DQ |
shift right |
KSHIFTR? k1, k2, imm8 k1 ← k2 >> imm8 |
(V5+BW | (V5+BW | (V5 | (V5+DQ |
test |
KTEST? k1, k2 *2 |
(V5+BW | (V5+BW | (V5+DQ | (V5+DQ |
unpack |
KUNPCK?* k1, k2, k3 *3 |
N/A |
KUNPCKDQ (V5+BW |
KUNPCKWD (V5+BW |
KUNPCKBW (V5 |
xnor |
KXNOR? k1, k2, k3 k1 ← ~(k2 ^ k3) |
(V5+BW | (V5+BW | (V5 | (V5+DQ |
xor |
KXOR? k1, k2, k3 k1 ← k2 ^ k3 |
(V5+BW | (V5+BW | (V5 | (V5+DQ |
*1 or test: Calculate (k1 | k2). If all bits are ZEROs, set ZF. If all bits are ONEs, set CF.
*2 test: If all bits of (k1 & k2) are ZEROs, set ZF. If all bits of ((~k1) & k2) are ZEROs, set CF.
*3 unpack: Concatinate lower n-bit of k2 and lower n-bit of k3, set the double length bits to the lower bits of k1. (The bits from k2 comes upper.)
Upper bits of the destination K register are zeroed.
TIP: xnor instruction can be used for setting all bits. (Specify one K register for all 3 operands.)