PSLLQ - Packed Shift Left Logical Qword
PSLLQ xmm1, imm8 (S2 the number of bits is specified by imm8.
__m128i _mm_slli_epi64(__m128i m, int count) the number of bits is specified by count.
PSLLQ xmm1, xmm2/m128 (S2 the number of bits is specified by the lower QWORD of xmm2/m128.
__m128i _mm_sll_epi64(__m128i m, __m128i count) the number of bits is specified by the lower QWORD of count
For each QWORD, shift the bits to the left by the specified number of bits. Emptied lower bits are zeroed.
VPSLLQ xmm1, xmm2, imm8 (V1 the number of bits is specified by imm8.
__m128i _mm_slli_epi64(__m128i m, int count) the number of bits is specified by count.
VPSLLQ xmm1, xmm2, xmm3/m128 (V1 the number of bits is specified by the lower QWORD of xmm3/m128.
__m128i _mm_sll_epi64(__m128i m, __m128i count) the number of bits is specified by the lower QWORD of count.
VPSLLQ xmm1{k1}{z}, xmm2/m128/m64bcst, imm8 (V5+VL the number of bits is specified by imm8.
__m128i _mm_mask_slli_epi64(__m128i s, __mmask8 k, __m128i m, unsigned int count) the number of bits is specified by count.
__m128i _mm_maskz_slli_epi64(__mmask8 k, __m128i m, unsigned int count) the number of bits is specified by count.
VPSLLQ xmm1{k1}{z}, xmm2, xmm3/m128 (V5+VL the number of bits is specified by the lower QWORD of xmm3/m128.
__m128i _mm_mask_sll_epi64(__m128i s, __mmask8 k, __m128i m, __m128i count) the number of bits is specified by the lower QWORD of count.
__m128i _mm_maskz_sll_epi64(__mmask8 k, __m128i m, __m128i count) the number of bits is specified by the lower QWORD of count.
For each QWORD, shift the bits to the left by the specified number of bits. Emptied lower bits are zeroed.
VPSLLQ ymm1, ymm2, imm8 (V2 the number of bits is specified by imm8.
__m256i _mm256_slli_epi64(__m256i m, int count) the number of bits is specified by count.
VPSLLQ ymm1, ymm2, xmm3/m128 (V2 the number of bits is specified by the lower QWORD of xmm3/m128.
__m256i _mm256_sll_epi64(__m256i m, __m128i count) the number of bits is specified by the lower QWORD of count.
VPSLLQ ymm1{k1}{z}, ymm2/m256/m64bcst, imm8 (V5+VL the number of bits is specified by imm8.
__m256i _mm256_mask_slli_epi64(__m256i s, __mmask8 k, __m256i m, unsigned int count) the number of bits is specified by count.
__m256i _mm256_maskz_slli_epi64(__mmask8 k, __m256i m, unsigned int count) the number of bits is specified by count.
VPSLLQ ymm1{k1}{z}, ymm2, xmm3/m128 (V5+VL the number of bits is specified by the lower QWORD of xmm3/m128.
__m256i _mm256_mask_sll_epi64(__m256i s, __mmask8 k, __m256i m, __m128i count) the number of bits is specified by the lower QWORD of count.
__m256i _mm256_maskz_sll_epi64(__mmask8 k, __m256i m, __m128i count) the number of bits is specified by the lower QWORD of count.
For each QWORD, shift the bits to the left by the specified number of bits. Emptied lower bits are zeroed.
VPSLLQ zmm1{k1}{z}, zmm2/m512/m64bcst, imm8 (V5 the number of bits is specified by imm8.
__m512i _mm512_slli_epi64(__m512i m, unsigned int count) the number of bits is specified by count.
__m512i _mm512_mask_slli_epi64(__m512i s, __mmask8 k, __m512i m, unsigned int count) the number of bits is specified by count.
__m512i _mm512_maskz_slli_epi64(__mmask8 k, __m512i m, unsigned int count) the number of bits is specified by count.
VPSLLQ zmm1{k1}{z}, zmm2, xmm3/m128 (V5 the number of bits is specified by the lower QWORD of xmm3/m128.
__m512i _mm512_sll_epi64(__m512i m, __m128i count) the number of bits is specified by the lower QWORD of count.
__m512i _mm512_mask_sll_epi64(__m512i s, __mmask8 k, __m512i m, __m128i count) the number of bits is specified by the lower QWORD of count.
__m512i _mm512_maskz_sll_epi64(__mmask8 k, __m512i m, __m128i count) the number of bits is specified by the lower QWORD of count.
For each QWORD, shift the bits to the left by the specified number of bits. Emptied lower bits are zeroed.
x86/x64 SIMD Instruction List
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