VPLZCNTQ - Packed Leading Zero CouNT Qword

PLZCNTQ xmm1{k1}{z}, xmm2/m128/m64bcst    (V5+CD+VL
__m128i _mm_lzcnt_epi64(__m128i a)
__m128i _mm_mask_lzcnt_epi64(__m128i s, __mmask8 k, __m128i a)
__m128i _mm_maskz_lzcnt_epi64(__mmask8 k, __m128i a)

For each QWORD, set the number of leading zero bits of (1) to (2).
PLZCNTQ ymm1{k1}{z}, ymm2/m256/m64bcst    (V5+CD+VL
__m256i _mm256_lzcnt_epi64(__m256i a)
__m256i _mm256_mask_lzcnt_epi64(__m256i s, __mmask8 k, __m256i a)
__m256i _mm256_maskz_lzcnt_epi64(__mmask8 k, __m256i a)

For each QWORD, set the number of leading zero bits of (1) to (2).
PLZCNTQ zmm1{k1}{z}, zmm2/m512/m64bcst    (V5+CD
__m512i _mm512_lzcnt_epi64(__m512i a)
__m512i _mm512_mask_lzcnt_epi64(__m512i s, __mmask8 k, __m512i a)
__m512i _mm512_maskz_lzcnt_epi64(__mmask8 k, __m512i a)

For each QWORD, set the number of leading zero bits of (1) to (2).
x86/x64 SIMD Instruction List  Feedback